Run transient analysis and you'll see Q toggling. Note that it only works because I set clock pulse width to16ns which is in between the 15ns minimum delay and 30ns maximum path delay. To complicate things it must be longer than then minimum delay of any of the gates, otherwise the pulse will be 'swallowed' by the inertial delay effect.Īttached is a working version of the case where J=K=1. In order for it to work (i.e be stable and not oscillate as you're experiencing) the clock pulse width must be shorter than the delay of CLK-to-Q path (delay through two NAND gates). The shown design of a JK flip flop does not work in practice for J=K=1 state. Honestly, i don't know if i can trust this software to simulate anything else. I wanted to buy the new version of MultiSim but seeing that a simple gated JK latch is too much for this software, i am losing faith. To verify if that was fixed in the newest version 12, i downloaded the latest educator's trial version 12 but the problem still persists. I am honestly very disappointed that such a simple and basic logic design is not being correctly simulated in MultiSim 11. I have recreated the exact same circuit in LiveWire and the latter simulates the circuit perfectly, and the characteristic table obtained corresponds perfectly to that in my textbook. I really believe that this is a major bug in the software itself. I have researched extensively and found several other threads on this forum about MultiSim not being able to correctly simulate JK FlipFlops based on logic gates. But the simulation simply refuses to work properly. I have fixed it and attached the correct circuit, together with the schematic from wikipedia. There was a mistake with your modified attachment in one of the SR latch gate inputs.

Jk flip flop multisim